The present invention relates to circuits for refreshing dynamic memory during a microprocessor sleep mode.
In personal computers which are portable and operate off batteries, it is desirable to be able to put the computer system into a "sleep" mode to reduce power consumption. It is not possible to simply turn off all the circuitry, since dynamic random access memories (DRAM) must periodically receive a refresh signal so that the memory contents will not be lost. Many systems use a microprocessor and a separate memory management unit for controlling accesses to DRAM. Since the memory management unit is interposed between the dynamic memory and the microprocessor, the microprocessor can simply be turned off (by removing its clock) and the memory management unit itself can control the refreshing of the DRAM. However, it is possible that additional DRAM memory may be inserted in the I/0 space of the system, where it would be directly coupled to the address and data bus of the microprocessor. Any dynamic memory connected to the microprocessor bus must either be refreshed by the microprocessor itself, or the microprocessor I/0 circuits must be put into a tri-state, high impedance condition so that external circuitry can take control of the bus and do the refresh operation. In order to enter the tri-state condition, the microprocessor must be activated and be receiving its clock signal, and thus cannot be in a sleep mode.